1. Field of the Invention
Embodiments of the present invention generally relate to memory devices. More particularly, embodiments of the present invention relate to delayed bitline leakage compensation circuits for memory devices.
2. Related Art
The storage capacity of memory devices continues to improve. This improvement is largely attributable to reduction in the minimum size of electrical components such as transistors, capacitors, and resistors, due to advanced semiconductor fabrication processes.
FIG. 1 illustrates a conventional memory device 100. As depicted in FIG. 1, the conventional memory device 100 includes a plurality of wordlines 10a–10d, a plurality of bitlines 20a–20c, and a plurality of memory cells 30a–30l. The wordlines 10a–10d are coupled to rows of memory cells while the bitlines 20a–20c are coupled to columns of memory cells. When a wordline is enabled, the memory cells coupled to the enabled wordline are provided access to bitline(s) coupled to these memory cells. Typically, the conventional memory device 100 supports read operations (where a bit is read from a memory cell) and write operations (where a bit is stored in a memory cell). Usually, the bit is either a “1” representing a logic high or a “0” representing a logic low.
Continuing with FIG. 1, the conventional memory device 100 has a plurality of precharge transistors 60a–60c, a plurality of sense amplifiers 40a–40c, and a plurality of keeper transistors 50a–50c. In this configuration, each bitline 20a–20c is coupled to a precharge transistor, a sense amplifier, and a keeper transistor. Moreover, the sense amplifiers 40a–40c are implemented as inverters. The precharge transistors 60a–60c and keeper transistors 50a–50c are implemented as PMOS transistors.
For a read operation, the bitlines 20a–20c are precharged to a predetermined value by the precharge transistors 60a–60c activated by a precharge bitline signal 70. For example, the predetermined value may be “1” (logic high). The keeper transistors 50a–50c provide noise immunity and help to maintain the bitlines 20a–20c at the predetermined value. If the predetermined value is “1” (logic high), each output of the sense amplifiers 40a–40c is “0” (logic low).
Then, one of the wordlines 10a–10d is enabled. The memory cells coupled to the enabled wordline (e.g., wordline 10a) are provided access to the bitlines 20a–20c. For instance, if memory cell 30a starts to discharge bitline 20a, the sense amplifier 40a will sense this discharge at its input and will change its output from a “0” (logic low) to a “1” (logic high), turning off the keeper transistor 50a. Hence, a “1” is provided as the output from bitline 20a for the read operation. On the other hand, if memory cell 30a does not discharge bitline 20a, the sense amplifier 40a will maintain its output at a “0” (logic low), assisted by the keeper transistor 50a. Hence, a “0” is provided as the output from bitline 20a for the read operation.
Ideally, the memory cells 30b–30d should not affect the bitline 20a since wordlines 10b–10d have not been enabled. However, instead of simply being in an off state, the memory cells 30b–30d also discharge the bitline 20a due to leakage current. Although the leakage current is small relative to the current available when the memory cell is in an on state when selected via a wordline, the leakage current is increasing as the size of the transistors is reduced. This leakage current can discharge the bitline 20a even though the selected memory cell 30a does not discharge bitline 20a. Additionally, the greater the number of memory cells coupled to the bitline 20a the greater the likelihood that the unselected (off state) memory cells will discharge the bitline 20a sufficiently to cause the sense amplifier 40a to undesirably sense this discharge at its input and to undesirably change its output from a “0” (logic low) to a “1” (logic high), turning off the keeper transistor 50a. Thus, an erroneous or false “1” will be provided as the output from bitline 20a for the read operation when the output should have been “0”.
Solutions to this leakage current problem have focused on resizing the keeper transistor and have been inefficient. Because of cost and limited space, it is difficult to make the keeper transistor large enough to counteract the bitline discharge caused by the leakage current. Moreover, the greater the size of the keeper transistor the slower the bitline is discharged by a selected memory cell, leading to performance issues.